Senior Timing Engineer

Santa Clara Valley (Cupertino), California, United States
Hardware

Summary

Posted:
Weekly Hours: 40
Role Number:200201812
At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. As Senior Timing Engineer, your primary responsibility will be the full chip and block-level timing closure of complex mixed-signal ASIC design. Dynamic, smart people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver the next groundbreaking Apple product.

Key Qualifications

  • At least 10+ years experience in ASIC design flow
  • Expertise in STA tools, e.g., PrimeTime
  • Hands-on experience in timing/SDC constraints generation and management
  • Proficient in scripting languages, especially Tcl
  • Knowledge of timing corners/modes, process variations, and signal integrity-related issues
  • Knowledge in logic optimization, synthesis, static timing analysis, and floor planning
  • Familiarity with synthesis, logic equivalence, DFT, and backend-related methodology and tools
  • Familiarity with digital top integration flows/methodology/checks
  • Experience in the full-chip STA of multiple successful tape-outs
  • Experience in low power design and implementation technique (e.g., power islands), knowledge of UPF, and power intent verification
  • Experience with script-based tool automation and familiarity with API’s and scripting languages for design tools such as Design Compiler, Genus, PrimeTime, etc… is a plus
  • Fluent with Synthesizable RTL Verilog and netlist

Description

• Full chip and block-level timing closure ownership throughout the entire project cycle (RTL, synthesis, and physical implementation) • Develop and maintain methodology and flows related to timing verification and closure • Generation of block and full chip timing constraints • Support digital chip integration work and flows • Work closely with Chip Architecture, Design Verification, Physical Design, DFT, and Power teams to achieve the first tape out success on designs • Work with multi-disciplinary groups to make sure designs are delivered on time and with the highest quality by incorporating accurate checks at every stage of the design process

Education & Experience

BSEE or MSEE

Additional Requirements