Design Verification Engineer
Santa Clara Valley (Cupertino), California, United States
At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, smart people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it. Join us to help deliver the next groundbreaking Apple product!
- At least 5 years of SoC full chip/block level verification experience
- Knowledge of Wireless PHY DFE and/or Wireless Radio controller verification is a big plus
- Advanced knowledge of standard ASIC design and verification flows, simulation and testbench development
- Advanced knowledge of SystemVerilog and the UVM methodology
- Solid verification skills in problem solving, constrained random testing, coverage closure, gate level simulations, X propagation
- Experience writing scripts in languages such as Perl or Python
- Team player with excellent communication skills and the desire to take on diverse challenges
Testbench development, directed/constrained random test generation, failure analysis and resolution, coverage analysis, and flow development. Run RTL and gate level functional verification, debug failures, lead bug tracking, and analyze and close coverage. Work closely with the design and systems engineering teams to review specifications and architecture, extract features, define verification plan & coverage model. Support mixed-signal co-simulation using Verilog models of analog IP. Develop testbench, test cases, reference model, coverage model and automation of regression suite.
Education & Experience
BSEE or MSEE and 5 years of relevant experience