Wireless Design Verification Engineer
Santa Clara Valley (Cupertino), California, United States
Apple's growing wireless silicon development team is responsible for developing the next generation of wireless silicon! In this role you will be responsible for ASIC pre-silicon verification of extremely complex high throughput communication PHY and Radio sub-systems. You will develop leading edge testbenches, enhance advanced methodologies, develop verification plans, debug functional tests, and utilize coverage analytics. You will be in the center of the organization impacting and influencing many cross-functional teams.
- Leadership experience verifying complex IP with a track record of robust ASICs.
- Experience verifying Wireless PHY or Radio subsystems required. Exposure to digital-radio sequencers, PLL controllers, and/or DSP is a plus.
- Advanced knowledge of ASIC verification flows with SystemVerilog and UVM.
- Experience developing testbenches from scratch, bringing up designs in simulation.
- Skills with constrained random testing, coverage closure, and RTL / gate simulations.
- Proficient in a scripting language such as Python, Perl, Bash or similar.
- Great teammate / mentor with excellent communication skills and the desire to seek diverse challenges.
- Knowledge of a wireless protocol preferred, e.g. WIFI / IEEE 802.11, Bluetooth or LTE.
This role will empower you to lead critical block or sub-system verification of PHY and/or Radio Controller (digital), and architect and develop testbenches and environments. You will create, simulate and debug test scenarios, and lead regressions and issue tracking. There will be collaboration with design and systems engineering teams to review specifications and architecture, extract features, and define verification plans. You'll drive coverage analysis and closure, and collaborate with / support digital + mixed-signal co-simulations using SystemVerilog analog behavioral models.
Education & Experience
BSEE or MSEE and 8+ years of proven experience.