SoC Physical Design Engineering Program Manager

Santa Clara Valley (Cupertino), California, United States


Role Number:200203348
Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it. Do you want to join us in these pursuits? Join us to help deliver the next groundbreaking Apple product! Apple's Hardware Technology Engineering Program Management Team is looking for an inventive, high-energy Engineering Program Manager (EPM) to work with our SoC Physical Design teams on the silicon used in our next-generation Apple products. In this position, you will work with the extended PD team and be involved in all phases of program execution, from early definition and planning through to delivery of final GDS. You will be responsible for coordinating the multiple PD teams to ensure efficient and on-time tapeouts. The PD EPM is an individual contributor position that uses outstanding communication, leadership and program management skills to align the various PD teams and problem-solve across multiple projects, technologies, and sites. This is an extraordinary opportunity to engage in cutting edge technologies and chip into groundbreaking Apple products year after year.

Key Qualifications

  • 13+ years of experience leading Silicon / SoC projects or a combination of Program Management and Physical Design experience.
  • Consistent track record of having taped out a number of sophisticated chips, from gates to GDS.
  • Knowledgeable about partition-level P&R implementation, including floorplanning, clock & power distribution, timing closure, physical and electrical verification.
  • Knowledgeable about Static Timing Analysis and the techniques used for timing closure and noise avoidance / fixing across multiple library corners.
  • Experience with large SoC designs (>20M gates) with frequencies in excess of 1GHz.
  • Experience with advanced process technology nodes.
  • Work with multi-functional teams, internal and external, and to balance multiple projects concurrently with very ambitious schedules.
  • Strong analytical skills with the ability to prioritize tasks and make critical decisions.


• Work closely with the Physical Design team across multiple sites and geographies. • Coordinate project-level headcount allocation across the PD organization. • Engage with Architecture, Design, and PD teams in order to optimize IP hardening across programs. • Lead multi-functional PD issue resolution and long-term initiatives. • Lead PD work, including early definition, tracking of metrics and schedules and alignment with program-level status. • Collect and maintain PD compute and storage requirements & usage.

Education & Experience

• MS or BS Degree in a technical subject area.

Additional Requirements