CSM Digital Design Engineer Lead

Santa Clara Valley (Cupertino), California, United States


Role Number:200204542
Are you a leader? Do you want to utilize your engineering background to make big things happen? Can you influence, connect, get results and communicate effectively? Can you deliver on a predictable and dynamic schedule? We have an extraordinary opportunity for a silicon design engineer to drive and lead technical engagements between Apple and silicon suppliers working on groundbreaking technologies. The Apple Custom Silicon Management Group provides critical custom silicon for all mobile products including iPhone, iPad, Apple Watch, and AppleTV. We are looking for a remarkable Digital Design Lead to work with multi-functional teams and external vendors to define, develop and productize the next generation of custom silicon solutions.

Key Qualifications

  • We are seeking applicants with 10+ years of digital design experience on complex multi-million gate architectures; mixed signal experience is highly desired.
  • Having achieved multiple tape-outs reaching production with first pass silicon.
  • 3+ years with managing digital design teams preferred.
  • Ability to drive and improve digital design methodology to achieve high quality first silicon.
  • Hands on experience with FPGA emulation, silicon bring-up, characterization and debug.
  • Able to work with multi-functional teams within Apple and external vendors across geographical boundaries to resolve architectural and implementation challenges with an eye towards schedule.
  • Strong verbal and written communication skills.


You will be responsible for assisting in architecture, implementation, verification, emulation and validation of custom silicon, including: - Working with Platform Architecture and Systems teams to establish silicon requirements. - Making appropriate design Trade offs balancing risk, area, power, performance and schedule. - Help improve engineering requirement specification documents for custom silicon. - Work with external vendors in developing micro-architecture, verification and emulation of custom silicon. - Drive vendor’s methodology to meet World Class silicon design standards. - Target to achieve bug free first silicon to meet bold product schedules.

Education & Experience

BSEE / MSEE is required

Additional Requirements

  • Some travel required.