ASIC IO Design Verification Engineer
Santa Clara Valley (Cupertino), California, United States
Imagine what you could do here. At Apple, great ideas have a way of becoming phenomenal products, services, and customer experiences very quickly. The high-speed serial interfaces of our chips are the critical information pipeline to other chips in the system. As a team member, you will craft models of these interfaces, devise new approaches to test those interfaces, and collaborate to find solutions to any design flaws before silicon fabrication.
- Deep understanding of USB or PCI Express.
- Familiarity with all aspects of pre-silicon design verification.
- History of building high quality UVM based verification environments.
- Deep understanding on constrained random verification techniques.
- Knowledge of functional coverage.
- Knowledge of assertion methodology.
- Excellent interpersonal skills and the dream to face diverse challenges.
As part of the IO verification team you are at the heart of the chip design effort collaborating with all silicon engineering disciplines to get functional and secure products to millions of customers quickly. You will be responsible for ensuring the quality of the system-on-a-chip and expected to architect testbenches, define methodology, coverage plans, test plans, tests. You will work with design and micro-architecture teams to understand the functional and performance goals of the project. You will evaluate design specs as they are written, conduct verification plan reviews, develop block level tests and triage failures. Your diplomatic skills will be required to find collaborative approaches to resolve bugs you find while owning the verification efforts in your area of the design. You will also need to balance our team goals while coordinating engineering efforts across the diverse teams that use our hardware.
Education & Experience
BSEE or BSCS required, Master’s or PhD desired.