ASIC Design Engineer — Fabric/Interconnect
Santa Clara Valley (Cupertino), California, United States
Does making the next extraordinary technology product excite you? Imagine what you could do here. We bring passion and dedication to our job and when you are a part of our team there's no telling what you could accomplish. At Apple, new ideas have a way of becoming excellent products, services, and customer experiences very quickly. Apple is leading the charge in high performance mobile computing with state of the ART SOC's announced with each of its revolutionary new product offerings. At the core of all Apple mobile SOC's, is an on-chip system interconnect bus that supplies the SOC agents with their requested load and store data from on chip and off chip memories. With every generation the max bandwidth, lowest latency, lowest area, and lowest power requirements are more stringent and require complex planning in order to achieve on Apple's schedules. Be part of the team building the architecture and design for the on-chip system interconnect bus for next generation Apple SOC's.
- RTL Logic Design in multi-million gate ASICs with Verilog or System Verilog.
- Hands on experience in all aspects of the ASIC development process with proficiency in front-end tools and methodologies
- Experience in writing specifications.
- Experience with multiple clock domains and asynchronous interfaces
- Experience or knowledge of system architecture, CPU & IP integration, power and clock domains
- Ability to communicate effectively across many internal groups
- Familiarity with software and operating systems concepts
- Expertise in:
- Computer Architecture concepts
- SoC system bus/fabric/interconnect design
- Memory controller design
- Networking packet based bus protocols
- Timing closure at high frequencies is a plus
- Familiarity with scripting languages such as Perl, Python
- Self-starter and highly motivated
As a member of the SoC Design team, you will be responsible for the following: Microarchitecture and design high-performance (low-latency, high-bandwidth, high-frequency), low-power on-chip fabric/interconnect and fabric components Analyze and configure fabric components to meet topology, bandwidth and latency needs of SoC Integrate fabric components at SoC level and sub-system level, including instantiation, connectivity, perform structural checks (such as Lint, CDC)) Synthesis and timing closure Power analysis of design components (using industry standard tools) Optimize design components for power and performance Develop and maintain methodology/flows/checks for designs Work with multi-disciplinary groups to deliver designs on time with the highest quality
Education & Experience
Bachelor's or Master's in EE/CS is required