SOC QoS Performance Engineer

Santa Clara Valley (Cupertino), California, United States


Role Number:200206214
Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish! Join us to help deliver the next groundbreaking Apple product. In this role, you will be a member of the system-on-chip (SOC) performance team, working within the hardware technology group to shape the architecture of Apple's future devices. Our team initiates and fosters deep collaboration between the SOC architecture, design, power, and software teams, to deliver world-class network-on-chip and caches/memory system quality-of-service. The end goal is to provide the best customer experience on the planet by enabling all the CPUs, GPUs, Machine Learning, Camera, Display, and Connectivity components on our chips to work seamlessly together. We are seeking an energetic and highly motivated SOC performance engineer to drive development of our on-chip communication interconnect and memory Quality-of-Service features.

Key Qualifications

  • Deep C++ programming knowledge
  • Coursework and understanding of computer architecture and the HW/SW stack
  • Coursework and/or practical experience with performance modeling and debugging
  • Coursework and/or practical experience with scripting for automation and data visualization
  • Ability to study a problem in depth, design experiments, analyze data, and present results
  • Examples of substantial HW or SW projects brought to completion


You will help create a full-chip C++ simulator for iPhone/iPad/Mac/Apple Watch SoCs. You will model new, emerging workloads such as Augmented Reality (AR) and Machine Learning (ML). You will use these models to study a range of performance and power trade-offs in our SoCs. Your work will be highly visible and critical for driving architecture improvements in Apple’s future products. Your responsibilities will include: - Learning about the state of the art in SoC IP and chip-level architecture - C++ modeling of graphics, camera, and ML dataflows, and integration with other SoC models - Running performance simulation of future applications - Careful analysis and presentation of simulation results - Tuning and validating future SoC HW/SW for the best user experience - Collaboration with cross-functional modeling, hardware, and software teams

Education & Experience

- BS or MS or PhD in CS, EE, or related field

Additional Requirements