SerDes Circuit Design Engineer
Portland, Oregon, United States
In this role, you will actively work within Analog-Mixed/Signal design team and participate in bring-up of embedded circuits; collaborating with many disciplines to enable the world’s premiere products. You will closely work with a talented group of Analog-Mixed/Signal designers working diligently to deliver hard IPs to Apple’s products while exceeding the highest expectations of quality, innovation and efficiency. At Apple, we work every single day to craft products that enrich people’s lives. And in doing so face challenges as SOC/PHY design complexity. If you have strong fundamentals and a track record of tackling technical challenges. If you are passionate about learning new skills and improving the value of your work. If you like to be tuned to the bigger-picture while diving deeply into the details to innovate and tackle problems! We have an opportunity for a forward-thinking and especially hardworking analog mixed signal engineer with background in high speed serial links circuit blocks. As a member of our team with multifaceted strengths, you will have the rare and exciting opportunity to work on upcoming products that will surprise and delight millions of Apple’s customers. And all of this while enjoying a strong culture where you own your career!
- The ideal candidate should have deep understanding of analog mixed-signal design with experience in high-speed serial links.
- Solid understanding and experience of designing analog mixed signal circuit blocks including Bandgap, biasing circuits, LDO regulators, amplifiers, comparators, switched-cap circuits, ADCs, DACs, Oscillators, Filters
- In-depth knowledge of analog mixed-signal concepts like mismatch mitigation, linearity, stability, low-power and low-noise techniques
- Experience with Tx/Rx equalization techniques and circuits like de-emphasis, CTLE, DFE
- Experience with high speed digital circuits (e.g., serializer, deserializer, counters, dividers, etc.)
- Familiarity with CDR architectures and implementations
- Design experience in advanced CMOS technologies, design with FinFet technology
- Hands-on experience with AMS IC development from definition to high-volume production including layout supervision, bench evaluation, correlation, and characterization
- Experience in lab testing of high-speed serial links
- Knowledge of common high-speed SerDes protocols (e.g., PCIe, USB, SATA, etc.)
- EXPERIENCE IN THE FOLLOWING AREAS IS DESIRABLE:
- Static timing analysis tools (e.g., Nanotime, Primetime, etc.)
- Modeling of digitally assisted analog adaptive loops (using C, Matlab or Python, etc.)
- Able to build VerilogA/AMS behavioral models
- Able to analyze and lead characterization data from lab and volume testing
- Knowledge of ESD requirements
We have ownership AMS circuits used in SerDes PHY, including evaluation of different circuit topologies for specific product requirements (e.g., Rx, CDR, Tx, bias generator, clock generation and distribution, etc.) You will be working with multi-functional teams to define requirements/specs (e.g., modeling, package, board, DFT, ESD, etc.), crafting block-level specifications based on link-budget, behavioral modeling, and transistor-level feasibility. You will also drive mask design to implement layout view of designs. We also are working on Generation/QA of various IP Kit views/files for release to IP consumers, defining production/bench-level testplans, and conducting design reviews of blocks with peers/management to show design meets spec targets and requirements.
Education & Experience
MSEE with 5+ years or PhD with 3+ years of proven experience. Apple is an Equal Opportunity Employer that is committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities. Apple will not discriminate or retaliate against applicants who inquire about, disclose, or discuss their compensation or that of other applicants.