Senior CPU Clock Engineer

Santa Clara Valley (Cupertino), California, United States


Role Number:200219711
Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Do you want join us in these pursuits? Join us to help deliver the next groundbreaking Apple product! We are looking for a strong candidate to join our CPU team focusing on clock distribution design, analysis, and implementation. In this highly visible role, you will be collaborating with multiple groups with a critical impact on the design of an industry leading CPU.

Key Qualifications

  • You should possess 8+ years of high-speed clock design and implementation experience
  • Proven experience in high frequency clock distribution design, implementation, and analysis
  • Strong understanding of deep sub-micron process technology and circuits
  • In-depth knowledge of Spice models and Spice simulation/analysis tools
  • Good understanding of STA fundamentals, clock-related timing parameters, and EMIR/SIGEM analysis
  • Strong scripting and automation skills using Tcl/Perl. Knowledge of python is a plus
  • Working knowledge and familiarity with std cell architectures
  • Knowledge of industrial standards and practices on physical design, analysis, and physical verification
  • Self-motivated problem-solver with an ability to work well in a team setting


As a CPU Clock Lead, you will be required to work on the following: • Comprehend product requirements and translate them to CPU clock specifications • Clock physical design planning and analysis • Engage with block designers on the physical design aspects of clocking • Collaborate with global teams on std cells, clock construction, and timing analysis flows

Education & Experience

MS or PhD in Electrical Engineering is required.

Additional Requirements