PHY RTL Design Engineer

Santa Clara Valley (Cupertino), California, United States


Role Number:200229822
Come join Apple’s growing wireless silicon development team. Our wireless SOC organization is responsible for all aspects of wireless silicon development. With a particular emphasis on highly energy-efficient design and new technologies that transform the user experience at the product level, all of which is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture, and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. If you enjoy a fast-paced and challenging environment and collaborating with people across different functional areas as well as thriving during crisis times, we encourage you to apply. We are looking for Physical Layer design engineers to design and implement advanced signal processing algorithms for Wireless LAN communication systems. Primary job responsibility is the architecture, design and verification of 802.11ac physical layer algorithms. In this role you will interact with protocol, software and systems teams to develop state-of-the-art wireless silicon for applications in Apple products.

Key Qualifications

  • Ideally at least 7 years of industry experience in wireless PHY design engineering
  • Strong fixed-point knowledge and extensive experience with bit-true cycle-accurate verifications
  • Understanding of Decoders - Viterbi, LDPC, Polar
  • Understanding of Filter design, multi-radix implementation and compromises
  • Knowledgeable in modern design techniques and energy-efficient/low power logic design and power analysis
  • Familiarity with power estimation (vector-less and vector-based), modeling, profiling, and post silicon power correlation
  • Solid understanding of wireless standards, such as IEEE 802.11, 802.15, Bluetooth or 3GPP is a plus
  • Background in computer architecture
  • Bus fabric, especially APB/AHB/AXI
  • Power management with multiple power domainsPower management with multiple power domains
  • Proven track record of bringing logic designs into high volume production
  • Ability to work well in a team and be productive under ambitious schedules
  • Should exhibit excellent communication skills and be self-motivated and well organized
  • Experience with FPGA and/or emulation platform desired
  • Excellent communications skills – both written and oral


Develop signal processing intensive design for wireless communication SoCs, including: - Writing specifications, other documents and defining Microarchitecture based on MATLAB/C system model - Architecting area and power efficient low latency designs with scalabilities and flexibilities - Work with algorithm and software team to ensure performance and power efficiency - Power and Area efficient RTL logic design, and DV support - Running tools to ensure lint-free and CDC/RDC clean design - Synthesis and timing constraints - Experience in design of signal processing Wireless protocols including 802.11 a/b/g/n/ac

Education & Experience

MSEE or Ph.D. preferred

Additional Requirements