Senior Timing Engineer

Santa Clara Valley (Cupertino), California, United States


Role Number:200230402
Come join Apple’s growing wireless silicon development team. Our wireless SOC organization is responsible for all aspects of wireless silicon development. With a particular emphasis on highly energy-efficient design and new technologies that transform the user experience at the product level, all of which is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture, and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. If you enjoy a fast-paced and challenging environment and collaborating with people across different functional areas as well as thriving during crisis times, we encourage you to apply.

Key Qualifications

  • At least 10+ years experience in ASIC design flow
  • Expertise in STA tools and flow
  • UPF flow for power islands as well as voltage islands
  • Knowledge of timing corners/modes, process variations, and signal integrity-related issues
  • Hands-on experience in timing/SDC constraints generation and management
  • Proficient in scripting languages (Tcl and Perl)
  • Familiarity with synthesis, logic equivalence, DFT, and backend-related methodology and tools
  • Knowledge in logic optimization, synthesis, static timing analysis, floor planning
  • Fluent with RTL Verilog/VHDL
  • Familiarity with digital top integration flows/methodology/checks
  • Experience with script-based tool automation and familiarity with API’s and scripting languages for design tools such as Design Compiler, PrimeTime, etc… is a plus


- Full chip and block-level timing closure ownership throughout the entire project cycle (RTL, synthesis, and physical implementation) - Develop and maintain methodology and flows related to timing verification and closure - Generation of block and full chip timing constraints - Experience in low power design and implementation technique, knowledge of UPF, and power intent verification - Support digital chip integration work and flows - Work closely with Chip Architecture, Design Verification, Physical Design, DFT, and power teams to achieve the first tape out success on designs - Work with multi-disciplinary groups to make sure designs are delivered on time and with the highest quality by incorporating accurate checks at every stage of the design process

Education & Experience

MSEE or Equivalent required

Additional Requirements