Senior Synthesis & Timing Engineer
San Diego, California, United States
Come and join Apple’s growing wireless silicon development team. Our wireless SoC organization is responsible for all aspects of wireless silicon development, emphasizing highly energy-efficient design and new technologies that transform the user experience at the product level. All of this is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. If you enjoy a fast-paced and challenging environment, collaborate with people across different functional areas, and thrive during crisis times, we encourage you to apply.
- This position requires thorough knowledge of the ASIC design flow, synthesis, static timing analysis, scripting, and netlist generation.
- The ideal candidate will have the following background:
- 10+ years experience in the ASIC design flow.
- Expertise in STA tools and flow.
- UPF usage for power and voltage islands.
- Logic synthesis execution for optimal PPA using physically aware techniques in single-digit process nodes using Design Compiler, Fusion Compiler &/or Genus.
- Hands-on experience in timing/SDC constraints generation and management.
- Knowledge of timing corners, operating modes, process variations, and signal integrity-related issues.
- Proficient in scripting languages (Tcl and Perl).
- Competent in the closure of end-to-end logic equivalence (FV, LEC) with functional ECOs in the mix.
- Familiarity with DFT and backend related methodology and tools.
- Fluent with RTL Verilog/VHDL.
- Familiarity with digital top integration flows/methodology/checks.
- Experience with script-based tool automation and familiarity with API’s and scripting languages for design tools such as Design Compiler, Genus, PrimeTime, etc. is a plus.
As a Senior Timing Engineer, you will work in a team developing Wireless SoCs with custom hardware accelerators and multiple ARM-based sub-systems. You will work closely with SoC architects and IP developers to develop SoCs that meet Apple devices' power, performance, and area goals. You will help define the processes, methods, and tools for designing and implementing these large, complex SoCs. Collaboration with multi-disciplinary groups will be needed to make sure designs are delivered on time and with the highest quality by incorporating precise checks at every stage of the design process. In this highly visible role, you will be at the center of the ASIC creation effort, interfacing with all disciplines, with a critical impact on getting leading-edge products out to delight millions of customers. • Full chip and block-level timing constraint and closure ownership throughout the entire project cycle (RTL, synthesis, and physical implementation). • Execute low power design and physical synthesis techniques, deploying knowledge of UPF and power intent verification. • Deploy and enhance methodology and flows related to timing constraint verification and timing closure. • Generation of consistent block and full chip timing constraints. • Support digital chip integration work and flows. • Work closely with Chip Architecture, Design Verification, Physical Design, DFT, and power teams to achieve the first tape out success on designs - generally bridging the RTL and place & route worlds. • Work with multi-disciplinary groups to make sure designs are delivered on time and with the highest quality by incorporating proper checks at every stage of the design process.
Education & Experience
MSEE or Equivalent required
- Apple is an equal opportunity employer that is committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities. Apple will not discriminate or retaliate against applicants who inquire about, disclose, or discuss their compensation or that of other applicants.