Wireless SoC Design Integration Engineer

Santa Clara Valley (Cupertino), California, United States


Role Number:200230414
Come join Apple’s growing wireless silicon development team. Our wireless SOC organization is responsible for all aspects of wireless silicon development. With a particular emphasis on highly energy-efficient design and new technologies that transform the user experience at the product level, all of which is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture, and design, Systems/PHY/MAC architecture, and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. If you enjoy a fast-paced and challenging environment and collaborating with people across different functional areas as well as thriving during crisis times, we encourage you to apply. As a Senior SoC Integration Design Engineer, you will work in a team developing Wireless SoCs with custom hardware accelerators, as well as multiple ARM-based sub-systems. You will integrate industry standard and custom hardware IP into SoCs. You will work closely with SoC architects, IP developers to develop SoCs that meets the power, performance and area goals for Apple devices. You will help define the processes, methods and tools for design and implementation of large complex SoCs. You will develop and maintain methodology and flows checks for your design. Interact with our verification team to ensure appropriate validation and coverage goals are met. You'll ensure security assumptions for the chip are accurately implemented within the block/s. Collaboration with multi-disciplinary groups to make sure designs are delivered on time and with the highest quality by incorporating accurate checks at every stage of the design process. In this highly visible role, you will be at the center of ASIC Integration effort interfacing with all disciplines, with a critical impact on getting functional products to millions of customers quickly.

Key Qualifications

  • You bring at least 10+ years of experience
  • This position requires thorough knowledge of the ASIC design flow
  • Top level integration of connectivity, system bus, peripherals, and CPU IP
  • Strong experience in complex ASIC design and IP integration, with a focus on high performance, low area, and low power
  • Successful tape-outs of multiple complex, high-volume SoCs in advanced design nodes
  • Proficient in design methodologies and EDA tools for DFT, power, clocking and debug
  • Experience working with back-end tools including synthesis
  • Expert knowledge of ASIC design flow and netlist flow checks – Lint, CDC, Logical Equivalence
  • Expert knowledge of UPF flow for defining power intent of chips with multiple power domains
  • Understanding of multi-clock designs, power management, reset and power sequencing
  • Proficiency in one or more of the following highly desirable: PCIe, AXI/AHB bus fabric, ARM-based processor sub-systems


As a senior SoC Design/Integration engineer you will have responsibilities spanning all aspects of SoC: - Responsible for chip level design infrastructure - Evaluate standard hardware IPs for integration into new SoCs - Review architecture and design of custom IPs for integration into new SoCs - Design and develop interface logic and top level netlists for new SoCs - Develop and implement methodologies for I/O, DFT, debug, clocking and power - Responsibility includes feasibility, micro-architecture, RTL design, front-end implementation and post-silicon system bring-up - Implementation and verification of design in RTL and taking the design through all the FE flows - Ownership of the Integration Spec for the design project, integration and optimization of any memories and hard macros - Provide technical leadership through personal example, mentorship, and strong teamwork

Education & Experience

MSEE or Ph.D. preferred

Additional Requirements