Senior RFIC Design Lead
Santa Clara Valley (Cupertino), California, United States
Would you like to join Apple’s growing wireless silicon development team? The wireless RFIC team architects, designs, and validates radio transceivers integrated into complex wireless SoCs. Our wireless organization is responsible for all aspects of wireless silicon development that transform the user experience at the product level, all of which is driven by a best-in-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. In this highly visible role, you will be at the center of a wireless SoC design group with a critical impact on getting Apple’s state-of-the-art wireless connectivity solutions into hundreds of millions of products.
- Typically requires 15+ years of RF/analog and mixed-signal design experience, with 7+ years management experience in cutting-edge RF CMOS design.
- Direct experience in designing and bringing into mass production ZIF RF transceivers in deep sub-micron RFCMOS technology.
- Deep understanding of analog, mixed-signal and RF circuit design. This includes design of on-chip LNAs and PAs, PLL/VCO/DCO/LOGEN blocks, mixers, baseband filters and amplifiers, data converters and calibration methods associated with such high performance wireless systems and ZIF designs. Experience should also include understanding of DFT and DFM techniques for mass production environment.
- Deep understanding of analog design concepts such as analysis of noise, linearity, mismatch, stability and other analog impairments.
- Deep understanding of CMOS device physics, RF device modeling, device noise parameters and inductor modeling.
- Familiarity with various RF transceiver architectures and their trade-offs, system specifications and ability to work with system architects to translate system requirements into circuit requirements at IC level; strong understanding of impact of modulation type to radio architecture and requirements.
- Demonstrated capability to work with digital design group for an optimum partition between digital and analog domain.
- Familiarity with the integration flows and challenges of wireless SoCs.
- Familiarity with mixed-signal mode verification methodology (SystemVerilog, AMS, Nanotime).
- Strong knowledge of desense and able to work closely with board RF/HW/Antenna teams to optimize board/module layouts for desense mitigation. Also, has experience with desense mitigation with integrated PMUs/DSPs (i.e. substrate isolation, return loops, package isolation, frequency planning, etc).
- Familiarity with Cadence Virtuoso, Spectre RF, Matlab, EM simulation (EMX, HFSS) and similar tools.
- Extensive experience in Si characterization and debug.
- Ability to drive strong production test/QA methodologies.
- Extensive experience in IP sourcing and management.
As a Senior RFIC Design lead, you are going to be responsible for providing RFIC solutions for wireless SoC and driving them to mass production for Apple products. Responsibilities include: - Lead design of radio transceiver blocks and transceiver integration - Drive radio KPI (power, area, performance) to meet product requirements - Work with cross-functional teams including platform architecture, wireless design, SW to define radio features enabling wireless innovation - Work with technology team on process selection for the target device - Work with SoC integration teams to integrate radio transceiver and mixed-signal IPs into wireless SoC - Drive and enhance RFIC design methodology (system-level mixed-signal verification, RF chip/package/board de-sense) to achieve first-pass silicon success - Perform detailed radio bring-up/characterization and work with systems integration/test to solve issues and optimize wireless system performance - Work with product/test engineering teams to implement low-cost RF ATE - Consult on RF/analog issues across Apple
Education & Experience
MSEE required; PhD is preferred