RFIC Design Engineer
Santa Clara Valley (Cupertino), California, United States
Would you like to join Apple’s growing wireless silicon development team? The wireless RFIC team architects, designs, and validates radio transceivers integrated into complex wireless SoCs. Our wireless organization is responsible for all aspects of wireless silicon development that transform the user experience at the product level, all of which is driven by a best-in-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. As an RFIC design engineer, you will be at the center of a wireless SoC design group with a critical impact on getting Apple’s state-of-the-art wireless connectivity solutions into hundreds of millions of products.
- Typically requires at least MS + 4 years of experience or a PhD in the area of Analog / Mixed-Signal IC design with advanced CMOS technology nodes. We are open to multiple experience levels.
- Deep understanding of analog and RFIC circuit design.
- Direct tape out experience with one or more of the following blocks: on-chip LNAs and Pas, PLL/VCO/DCO/LOGEN blocks, mixers, baseband filters and amplifiers in deep sub-micron CMOS technology.
- Deep understanding of analog design concepts such as analysis of noise, linearity, mismatch, stability and other analog impairments.
- Deep understanding of CMOS device physics, RF device modeling, device noise parameters and inductor modeling.
- Familiarity with packaging effects, supply isolations, high frequency ESD structures, and circuit layout for optimum RF performance.
- Familiarity with various RF transceiver architectures and their trade-offs, as well as calibration methods used for different transceiver architectures.
- Understanding of system specifications and ability to work with system architects to translate system requirements into circuit requirements at IC level.
- Open to work with digital design group for an optimum partition between digital and analog domain.
- Familiarity with the integration flows and integration challenges of wireless SoCs.
- Familiarity with mixed-signal mode verification methodology (SystemVerilog, AMS, Nanotime).
- Knowledge of desense issues and able to work closely with board RF/HW/Antenna teams to optimize board layouts for desense mitigation. Experience with desense mitigation with integrated PMUs/DSPs (i.e. substrate isolation, return loops, package isolation, frequency planning, etc.).
- Familiarity with Cadence Virtuoso, Spectre RF, Matlab, EM simulation (EMX, HFSS) and similar tools.
- Experience in Si characterization and debug.
- Ability to drive strong production test/QA methodologies.
As an RFIC design engineer, you will be a key member of an RFIC design team, researching, designing and bringing the next-generation wireless SoCs into high-volume production at advanced CMOS technology nodes. Responsibilities include: - Design of analog and RF blocks inside the radio, starting from concept and transistor-level feasibility studies. - Overseeing the layout and verifying the design to ensure a successful tape-out. - Testing the design and debugging the issues that may arise from early development stages through productization. - Work with platform architects, system groups and digital design groups to define the requirements for RF and baseband blocks based on the system requirements. - Work with the technology team to understand the capabilities and limits of the technology node to achieve the optimum performance. - Participate in defining bench bring-up and test plans for validation and characterization of designs into mass production. - Provide guidance on analog and RF issues across Apple.
Education & Experience
MSEE is required. PhD is preferred