Graphics Formal Design Verification Engineer

Austin, Texas, United States


Role Number:200242178
Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You’ll ensure Apple products and services can seamlessly and expertly handle the tasks that make them beloved by millions. Joining this group means you’ll be crafting and building the technology that fuels Apple’s devices. Together, we will enable our customers to do all the things they love with their devices. The Graphics Verification Engineer will be responsible for the pre-silicon RTL verification utilizing formal and property checking methods. This includes deep understanding of the micro-architectural details of their block and how it works within the broader GPU design. A strong computer architecture background, preferably in graphics, and a proven foundation in verification methodology will be leveraged to close testing coverage with high confidence.

Key Qualifications

  • Work with the design team to review and enhance specifications
  • Develop verification plans in coordination with design leads, verification leads and micro-architects
  • Develop and complete formal verification across multiple design blocks
  • Conduct formal verification reviews with design and verification teams
  • Handle deliverables and work with multi-functional teams to support product requirements
  • Create automated flows and infrastructure for formal verification
  • Work with other block and core level engineers to ensure seamless verification flow


Advanced knowledge of CPU or preferably GPU design architectures, VLSI circuits, and digital logic design Experience in formal verification and analysis of pipelined micro-architectures, MMUs, and cache coherency control mechanisms Strong experience with formal verification tools, such as JasperGold, IFV, etc. Experience in using academic tools is a plus A deep understanding of abstraction techniques and formal verification technologies Knowledge and experience in reviewing and interpreting design specifications You will have experience with HDLs such as Verilog/System Verilog and temporal logic assertion-based languages such as SVA You will be proficient in programming/scripting languages with excellent debugging skills Knowledge of constrained random verification methods is a plus Excellent interpersonal skills and ability to collaborate

Education & Experience


Additional Requirements