ASIC Design Engineer
Santa Clara Valley (Cupertino), California, United States
In this role, you will actively work within the Analog/Mixed-Signal team to design and deliver hard IPs to Apple’s products. In this role, you will participate in digital design and analog mixed signal modeling for SoC/Wireless/Cellular with a focus on ADC/DAC/AFE system. As a member of our team, you will have the rare and phenomenal opportunity to work on upcoming products that will surprise and delight millions of Apple’s customers.
- Deep knowledge of RTL design
- Deep knowledge of Verilog and System Verilog
- Experience in System Verilog modeling for AMS blocks is a plus
- Good Knowledge of front-end tools (Verilog simulators, linters, clock domain crossing checkers)
- Good knowledge of Mixed signal concepts
- Good knowledge of Algorithm development
- Experience with transistor level implementation of digital circuits is a plus.
- Working experience with physical design teams
- Good knowledge of synthesis, static timing , DFT
- Experience of developing custom firmware is preferred
- Good knowledge of System-Verilog assertions, checkers and other design verification techniques are a plus
- Good knowledge of scripting languages. Perl and Python are plusses.
- Good communication and presentation skills
In this job, you will be responsible for designing blocks specified by you or others for advanced mixed signal circuits. You will also be responsible for specifying and micro architecting . You will be writing detailed design specification and will be in close collaboration with the system architect, circuit designers and design verification engineers. You will work on behavioral modeling of analog blocks and support design verification to ensure bug free silicon. You will also be working with the semi custom PD team for timing closure for your designs and finally supporting silicon bring up.
Education & Experience
MSEE with 4+ year experience (Preferred) or BSEE with 8+ year experience, or equivalent is required