GPU Physical Design Clocking Engineer
Austin, Texas, United States
Do you love building elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You’ll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices. Together, we will enable our customers to do all the things they love with their devices. This role requires a mix of strategic engineering along with hands-on, technical work. You will be responsible for implementing complete chip design from netlist to tapeout. You will have hands on experience in physical design and large chip integration.
- We value a successful track record in all aspects of ASIC integration including Floorplanning, Clock and Power distribution, global signal planning, I/O planning and hard IP integration.
- Experience planning, implementing, and analyzing high-speed clock distribution networks from the root to leaf. Exposure to different strategies for clock distribution including balanced trees, mesh, and forwarded clocks.
- Your practical knowledge with hierarchical design approach, top-down design, budgeting, timing and physical convergence will be an asset. Ability to comprehend the needs of Functional and Test clocking requirements in to design.
- Proven ability to use critical clock metrics revolving around latency, skew and variation to prevent and solve sophisticated cross-hierarchy clocking issues.
- Showcase your experience on the design and integration of clocking IP from both internal and external vendors and be able to specify and drive IP requirements in the physical domain.
- Your depth of expertise with large SoC designs (>20M gates) with frequencies in excess of 1GHz utilizing state of the art technologies will serve you well.
- Experience planning and crafting test structures to evaluate clocking functionality and performance post Silicon. Background in engaging with Test teams pre/post Silicon to debug and analyze problems from a clocking perspective.
- From a CAD tool perspective, experience with Floorplanning tools, P&R flows, global timing verification is required. Further, experience with SPICE simulation/analysis and Physical Design Verification Flows is a plus.
Work closely with the RTL/FE teams to understand chip architecture and drive clocking aspects early in design cycle. Drive best in class clocking construction and solutions for performance, power and Area (PPA). Collaborate to drive clocking methodologies and “best known methods” to streamline PD work, come up with guidelines and checklists, drive execution, and supervise progress. Be focal point for all things clocking, set goals and breakthroughs, plan short and long-term work, understand dependencies between different domains like top, STA, block place and route. Lead and resolve design and flow issues related to physical design, identify potential solutions and drive execution. Are you a confident problem solver who thrives under pressure to find new, creative solutions? Are you ready to help chart the future of Apple's ecosystem? If so, we are excited to hear from you!
Education & Experience
MSEE or equivalent is required