DRAM Validation Automation Engineer

Santa Clara Valley (Cupertino), California, United States


Role Number:200249681
Does an exciting, dynamic, fast paced and team oriented environment catch your attention? Do you love crafting sophisticated solutions to highly complex challenges? If so, consider joining us! We are seeking an DRAM Validation Automation Engineer to work on Apple's next groundbreaking SoC's. As part of our Silicon Technologies group, you will help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You will ensure Apple products and services can seamlessly and deftly handle the tasks that make them beloved by millions. Joining this group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices. Together, we will enable our customers to do all the things they love with their devices! In this position, we will be ensuring the successful development of SW/HW for DRAM validation with SoC devices. You will also be responsible for lab management.

Key Qualifications

  • Experience in silicon validation automation.
  • Experience in hardware and software debugging skill.
  • Programming experience in C, Tcl, Expect, Python…
  • Good background in computer architecture.
  • Basic knowledge in Bench tools (Oscilloscope, Logic Analyzers, Power Analyzers…)
  • Basic knowledge in DRAM cell architectures, DRAM memory organization and periphery design for low DRAM power.
  • Experience on system level DRAM validation.
  • Basic knowledge in memory test patterns.
  • Excellent communication skills and teamwork abilities.


• Work with design, product and validation engineers to ensure memory SW requirements. • Ensure that the DRAM SW meets Apple's product development and post ramp qualification schedule. • Develop DRAM validation/debugging SW tools. • Collaborate with the DRAM engineers for DRAM Lab solutions. • Technical support for the validation and qualification of DRAM. • Support debugging RMA material with apparent DRAM related defects. • Plan SoC/DRAM Lab HW/SW and tools and purchase them. • Bench tools and Lab management.

Education & Experience

BSEE / MSEE is required

Additional Requirements