Digital-Mixed-Signal Verification Engineer (f/m/d)
Linz, Upper Austria, Austria
At Apple, we work every single day to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a visionary and unusually talented Digital-Mixed-Signal Verification Engineer. As a member of our dynamic group, you will have the rare and rewarding opportunity to craft upcoming products that will delight and inspire millions of Apple’s customers every single day. Do your life’s best work here at Apple! This role is for a Digital-Mixed-Signal Verification engineer who will enable bug-free first silicon for the digital-/analog- and mixed-signal designs. The responsibilities include all phases of pre-silicon verification including: developing and verifying analog behavioral models (e.g. LNA, PLL, ADC, DAC, Mixer,..) in System Verilog at different abstraction levels, matching the schematic specifications till the pre-silicon sub-/system verification with main respect to Analog/Mixed-Signal macros in close collaboration with multiple disciplines. As a verification engineer you have ownership of functional analog macro sign-off which includes the communication of status and results into the existing verification management framework.
- Experience in analog design
- Experience with digital simulation tools like Cadence NCsim, Synopsis VCS, Mentor Modelsim and/or Mixed Signal simulation tools like Cadence AMS-Designer, Synopsis VCSXA, Mentor Questa
- Ability to read and understand schematics to define and implement functional behavioral models
- Ability to think on different abstraction levels from very detailed component to system-level
- 3+ years of experience in hardware description languages like System Verilog, VHDL, Verilog
- Outstanding sense and drive for quality of deliverables
- Verification mindset
- Reliable, ability to work independently as well as in a team environment
- Good interpersonal and communication skills
- Fluent English, spoken and written
- System know-how in the cellular RF transceiver domain is a plus
- C/C++ programming language for testcase development is a plus
Developing analog behavioural models in System Verilog Running model versus schematic correlation simulations to guarantee the matching to the schematic specifications Defining/verifying verification requirements Coding of test scenarios and assertions Doing sub-/system verification with existing UVM top level test benches Interacting with analog and digital design engineers, firmware engineers, RF layout engineers.
Education & Experience
Degree in Computer Science, Computer Engineering, Mechatronics, Electronics or equivalent Apple is an equal opportunity employer that is committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities.