ASIC Design Engineer – Fabric/Interconnect

Santa Clara Valley (Cupertino), California, United States
Hardware

Summary

Posted:
Role Number:200258246
Imagine what you could do here. At Apple, great ideas have a way of becoming excellent products, services, and customer experiences very quickly! At Apple, we're leading the charge in high performance mobile computing with state of the art SOC's announced with each of our ground-breaking new product offerings. At the core of all Apple mobile SOC's, is an on-chip system interconnect bus that supplies the SOC agents with their requested load and store data from on-chip and off-chip memories. With every generation the max bandwidth, the lowest latency, the lowest area, and lowest power requirements are more exacting and require sophisticated planning in order to achieve on Apple's schedules. Be part of the team creating the architecture and design for the on-chip system interconnect bus for next generation Apple SOC's!

Key Qualifications

  • The ideal candidate will have the following background:
  • Master’s degree in EE/CE/CS with 10+ years of work experience in ASIC design
  • RTL Logic Design in multi-million gate ASICs with Verilog or System Verilog
  • Hands on experience in all aspects of the ASIC development process with proficiency in front-end tools and methodologies
  • Experience in writing specifications
  • Experience with multiple clock domains and asynchronous interfaces
  • Experience or knowledge of system architecture, CPU & IP integration, power and clock domains
  • Ability to communicate effectively across many internal groups
  • Familiarity with software and operating systems concepts
  • Familiarity with scripting languages such as Perl, Python
  • EXPERTISE IN:
  • Computer Architecture concepts
  • SOC system bus/fabric/interconnect design
  • Memory subsystem design
  • Networking packet based bus protocols
  • Timing closure at high frequencies is a plus

Description

As a member of the SoC Design team, you will be responsible for the following: Analyze architectural requirements of next generation of on-chip fabric and define scalable interconnect components Microarchitecture and design high-performance (low-latency, high-bandwidth, high-frequency), low-power on-chip fabric/interconnect and fabric components Power analysis of design components (using industry standard tools) Optimize design components for power, performance and timing Develop and maintain methodology/flows/checks for designs Work with multi-disciplinary groups to deliver designs on time with the highest quality

Education & Experience

Bachelor's or Master's in EE/CS is required

Additional Requirements

  • Apple is an equal opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.
  • We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform essential job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation.