CAD Engineer - PDV

Santa Clara Valley (Cupertino), California, United States


Role Number:200264378
Do you love building elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You’ll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions! Joining this group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices. Together, you and your team will enable our customers to do all the things they love with their devices. As a member of our CAD team, you will architect, develop, maintain and improve physical design verification (PDV) flows. The role requires you to work on flow and runset development for various technology nodes and tool sets. Working alongside with CAD team, you will be collaborating with the custom digital/analog/mixed-signal design, physical design (PD) and chip integration teams. You will need to have a deep understanding of design rule checks (DRC) and layout versus schematic (LVS) runsets, writing from scratch and/or modify existing ones. Also you should have worked with Dummy Metal Fill generation and Design for Manufacturability (DFM) rules at different technologies.

Key Qualifications

  • Typically requires a minimum of 3 years of industry experience in Silicon chip design flows.
  • Good knowledge in Calibre/ICV runset coding for DRC/LVS/ERC is required.
  • Physical verification debug experience in various technology nodes is desirable.
  • Knowledge/scripting in programming languages such as Perl, Python, Tcl, Shell, Makefile and C.
  • Understanding in Silicon technology and experience with flow development.


- Develop, maintain and improve physical verification flows and methodology. - Coordinate the effort of validating flows, improving for custom checks and data generation. - Work with the design and PD teams to facilitate the chip design process. - Code custom PDV rule decks such as Electrical rule checks (ERC) and Programmable ERCs. - Collaborate with tool vendor and foundries for PDK performance enhancements.

Education & Experience

BS/MS in EE/CS/CE or equivalent

Additional Requirements