Power Integrity Engineer
Austin, Texas, United States
The Mac organization is looking for an outstanding engineer to support the system-level Power Distribution Network (PDN) design, analysis and validation aspects of Mac and Accessory products development. The engineer should have deep knowledge and familiarity with power delivery network design architecture, analysis and validation methods. The engineer will work with cross-functional teams to design and implement a power supply network solution, develop and validate impedance and droop targets and verify the quality of the power supply using lab and in-situ silicon measurements.
- You must have proven technical understanding of power supply architectures covering voltage regulator technologies, power distribution network (PDN) modeling, PCB design practices and trade-offs for PDN design and optimization.
- You should have a good understanding of multi-phase of Buck/Boost converter and LDO design principles, operating modes, and system integration careabouts.
- Working knowledge in 3D/2D EM simulation tools, electromagnetic modeling and
- transmission line theory is required.
- Skills with associated tools for 2.5D (PowerSI, SIWave, Sentinel-PI, nSys), 3D
- Full wave (HFSS, nWave), quasi-static tools (Q3D, nApex) is required.
- Relevant proven understanding of HSPICE, Spectre, AMS, and Simplis models
- for system-level transient droop analysis is also necessary.
- In this role, you will be expected to have understanding of die-package-board
- power delivery network co-design constraints and tradeoffs.
- Ability to work with multiple cross functional teams to make the right trade-offs on
- the system performance is a must.
The role involves pathfinding studies in silicon development phase where feedback is provided to silicon and packaging team on system integration tradeoffs. Ability to execute on target impedance analysis, transient voltage droop and phase margin/ stability analysis is required. The candidate is expected to guide and work closely with the system team on the component selections, for optimum power solutions with high and low load transient, at different performance state.The candidate is also expected to work closely with System Design teams to provide detailed layout strategy and guidelines during design execution phase.The candidates is also expected to work with HW Validation teams to develop test-suites to perform system-level validation for evaluation of design margins on the power domains. The roll includes the PI support through the specific project design process which can include system pathfinding and verification stages, and characterization reviews with continuing guidance through production and ramp.
Education & Experience
M.S. with 5-7 years experience, or PhD (preferred) with minimum of 3-4 years experience
- - Hands-on experiences on package or board layout with Cadence is a plus. The candidate with this skill is expected to perform proof of concept layout study with Cadence.
- - Experience with Perl, Python or other scripting languages is desired. MatLab Experience is a plus
- - Excellent documentation and communication skills, ability to work independently, a desire to mentor, and demonstrated ability to innovate are required.
- - Candidate is also expected to have demonstrated experience in driving initiatives that
- improved process, procedures, and result quality.