CAD Engineer - Physical Design Verification (PERC)
Santa Clara Valley (Cupertino), California, United States
Do you love building elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You’ll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions! Joining this group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices. Together, you and your team will enable our customers to do all the things they love with their devices. As a member of our CAD team, you will architect, develop, maintain and improve physical design verification (PDV) flows. The role requires you to work on flow and runset development for various technology nodes and tool sets. Working alongside the CAD team, you will be collaborating with the custom digital/analog/mixed-signal design, physical design (PD) and chip integration teams. You will need to have a deep understanding of design rule checks (DRC) and layout versus schematic (LVS) runsets, writing from scratch and/or modify existing ones. Also you should have worked with Dummy Metal Fill generation and Design for Manufacturability (DFM) rules at different technologies.
- Industry experience in Silicon chip design flows.
- Good understanding in rule coding in Programmable ERC (PERC) is required.
- Knowledge in various ESD methodologies and debugging such as latch-up, topology, current density and point-to-point resistance checks.
- Expertise in Calibre/ICV runset coding for DRC/LVS.
- Knowledge in scripting/programming languages such as Perl, Python, Tcl, Shell, Makefile and C.
- Understanding of Silicon technology and experience with flow development in advanced nodes.
- Code custom PDV rule decks in Programmable ERCs for circuit topology and ESD checks - Develop, maintain and improve all aspects of physical verification flow and methodology - Coordinate the effort of validating flows, improving for custom checks and data generation - Collaborate with tool vendor and foundries for PDK performance enhancements
Education & Experience
BS/MS in EE/CS/CE or equivalent.