Cellular RF Systems Engineer - Phase Locked Loop (m/f/d)
Linz, Upper Austria, Austria
At Apple, we work every single day to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We invite you to join our dynamic group, for the unique and rewarding opportunity to contribute to upcoming products that will delight and inspire millions of Apple’s customers every day. Apple's RF Systems Engineering team is looking for a passionate, independent expert with a proven track record in the area of phase locked loops. Our world-class team shapes the mobile market with forward-thinking concepts while being fully accountable for execution and commitments on timeline and quality. Come and deliver leading-edge phase locked loops (PLLs) for Apple’s wireless products that enable a unique customer experience!
- We would like you to have 3+ years of relevant experience in RF, including solid expertise in cellular PLL architectures.
- You have extensive experience in specifying, simulating and modelling PLLs and LO distribution including the mathematical background.
- You have strong understanding of frequency generation architectures, experience in analyzing crosstalk and coexistence scenarios and avoiding or mitigating them.
- You have in-depth knowledge of cellular radio standards (GSM, UMTS, LTE, 5G NR), regulatory, and carrier requirements including their implications on PLL specifications.
- Excellent communication skills, both written & verbal, would be very helpful.
In this role, you will be part of the best-in-class cellular RFSE Team. You will work closely with transmitter and receiver architecture teams, RF design teams, design and drive PLL innovations with focus on leading-edge performance under real-life conditions and clear differentiation from other solutions. YOUR DAILY WORK INCLUDES THE FOLLOWING TASKS: - Defining and specifying PLL and clocking architectures for FR1 and FR2 (mmW) - Break-down PLL system requirements into requirements for the PLL building blocks including phase noise budget. - Implementation and simulation of the PLL in the frequency-domain and in the time-domain using MATLAB and C++. - Develop algorithms to improve PLL phase noise performance and methods to reduce spurs. - Prepare specifications as input for design teams. - Implementation of bit-true MATLAB and C++ reference models for the digital design. - Align MATLAB and C++ models with measurement results.
Education & Experience
MSEE is the foundation of your successful career to date. We would prefer a Ph.D. in electrical engineering or equivalent.
- Apple is an equal opportunity employer that is committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities. Apple will not discriminate or retaliate against applicants who inquire about, disclose, or discuss their compensation or that of other applicants.
- We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform essential job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation.