Sr. Wireless System Engineer – Cross Layer and Functional Developments

Santa Clara Valley (Cupertino), California, United States
Hardware

Summary

Posted:
Role Number:200283660
Wireless communications technologies have evolved so much in the past few decades. New protocols have been introduced to the limited radio spectrum, as well as the complexity of the existing communication protocols have also been growing a lot. While the wireless radio environment gets more and more congested, the new generations of emerging applications are becoming more demanding in all of latency, efficiency and performances. In order to meet the demands and achieve robust and optimal performances in this congested radio environment, PHY, MAC and cross-layer and cross-functional algorithms are inevitably becoming more sophisticated. In this technical role, you will be at the center of a silicon design group responsible for wireless system design for state-of-the-art wireless SoC products. You will focus on leading the innovations of designing algorithms or mechanisms to achieve the requirements, mitigate the impact from interference of different protocols, and therefore ensuring the robust and optimal performance of the system to enable the new emerging applications. The design may possibly involve but not limit to coexistence management, interference avoidance from time/frequency allocation, dynamic desensing, spatial beam management, interactions with other wireless protocols if possible and other innovative ideas. They may involve PHY/MAC cross-layer and cross-functional algorithm designs, and the implementations often require both HW and SW. You will work with different teams to participate specifying the algorithms for the new product and applications. You will be responsible for working with team members to define the interface to the algorithms, studying and verifying the performance, and collaborating with the HW and SW engineers to get them implemented. You will also be responsible for pre-silicon validations and post-silicon bring-up of the designed algorithms.

Key Qualifications

  • Deep understanding and prior experience in designing signal processing and wireless communications systems.
  • In-depth knowledge on wireless communication system (OFDM/MIMO, etc), hands on experience on lab testing & characterization will be essential.
  • Deep understanding of communication theory & signal processing related algorithms design (such as timing recovery, signal estimation and detection, automatic gain control, RF impairment estimation and correction, channel estimation, equalization, coding theory, etc.)
  • Experience with multi-radio coexistence management
  • Experience with system optimization in congested radio environment through cross-layer designs
  • Knowledge on modem architecture and microprocessor architecture. Experience with FW design is a plus.
  • Experience and knowledge on emulation systems, and virtual platforms will be a plus.
  • Experience with Matlab or Python and/or C/C++ for algorithm development, modeling, and simulation.
  • Experience on bring up real silicon in lab, being able to efficiently use lab equipment (such as spectrum analyzer, signal generator, power meter, etc) is a plus.
  • Knowledge in existing wireless communication protocols: 5G/LTE/WCDMA/GSM, 802.11a/b/g/n/ac/ax/be, 802.11ad/ay or Bluetooth/BLE

Description

• Design and simulate state-of-the-art wireless communication system for very high data rate applications. • Implement system models and investigate innovative algorithms in PHY/MAC cross-layer to mitigate the impact of the impact of congested radio environment and achieve robust performance. • Discuss with product teams and come up with novel algorithms to satisfy the requirements from the emerging applications in a congested radio environment. • Perform simulations to prove the effectiveness of the designed algorithms, and validate them on emulation systems • Work with firmware designers to realize the software part of these methods with high efficiency software implementation • Work with digital designers to realize the hardware part of these methods with power and area efficient digital implementations. • Bring up, test and characterize the designed algorithms on real silicon in lab.

Education & Experience

MS with 10+ Years experience or Ph.D. with 7+ Years experience.

Additional Requirements