Design Verification Engineer
Santa Clara Valley (Cupertino), California, United States
At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish! We, at the Display Technologies Engineering team, work on the next generation of groundbreaking products using best in class tools, flows and methodologies. Come join our team and be a part of the excitement!
- Professional coding skills in Verilog or SystemVerilog.
- Sophisticated knowledge of standard ASIC design and verification flows including RTL design, simulation and testbench development, coverage analysis and constrained random testing.
- Advanced knowledge of HVL methodology like UVM/OVM is a big plus.
- Experience with SystemVerilog Assertion (SVA).
- Experience writing scripts in languages such as Perl or Python is a plus.
- Experience with Formal Verification is a plus.
As part of the verification team supporting Apple's Display Technologies portfolio for the next-generation of Apple products, you will work closely with Design and Architecture teams to review specifications and architecture, extract features and define verification plan including the coverage model. You will then execute on this plan through testbench development, directed/constrained random test generation, assertion-based verification, failure analysis and resolution, and coverage analysis and closure. You will run RTL and gate level functional simulations. You will also support mixed-signal co-simulation using Verilog models of analog IP, and develop testbench, test cases, reference model, coverage model and automation of regression suite. You will also have the opportunity to enhance the team’s methodology and flows.
Education & Experience
BSEE/BSCE + 10 years of relevant experience or MSEE/MSCE + 7 years of relevant experience.