Senior Foundry Interface Engineer – RF Productization Engineer
Santa Clara Valley (Cupertino), California, United States
Can you influence, connect, get results and communicate effectively? As part of our Silicon Engineering group, you will take imaginative and revolutionary ideas and figure out how to turn them into reality! You and your team will apply engineering fundamentals and start from scratch if needed, bringing forward-thinking ideas to the real world. You will work at an exciting silicon design group that is responsible for crafting state-of-the-art ASICs! We have an extraordinary opportunity for Foundry Interface Engineers.
- We are looking for applicants with at least 7+ years of experience in semiconductor process technology and manufacturing.
- Experience collaborating with foundries in the areas of RF product yield improvement and product qualification.
- Deep knowledge of CMOS technologies, particularly in the field of RF / Analog is critical.
- Experience with parametric WAT and Yield data analysis, and proficient with statistical data analysis tools.
- Good understanding of yield failure mechanisms and tools for root cause finding (EFA, PFA, Nanoprobe, etc.).
- Familiarity with reliability mechanisms and device-safe operating areas is a plus.
- Experience delivering new designs to production under a very aggressive schedule.
- Good data analysis, problem solving, and very strong interpersonal skills required.
Imagine yourself in our RF design effort, collaborating with design teams and providing technology support, with a critical impact on getting functional products to millions of customers quickly. In this highly visible role, you will be at the center of process technology problem solving, providing design enablement for key RF products. The primary focus of this position is collaborating with internal RF/ Analog design teams and semiconductor foundries. This is a hands-on, dynamic role requiring travel to foundries and development sites. Support new product introduction from design concept through production release. Key tasks are design of experiments, parametric and Yield data analysis. Drive process improvements at Foundry to improve product performance and yield. Drive Failure Analysis (PFA/ EFA) to understand root cause for yield marginality. Team up with foundry to define baseline process for optimal product performance and yield. Drive design fixes to address reliability marginality related to device, interconnect degradation. Manage and mitigate technology risks for multiple projects in parallel.
Education & Experience
BSEE / MSEE is required, PhD preferred.
- Travel availability is required.