Silicon Validation Engineer

Boston, Massachusetts, United States


Role Number:200292945
At Apple, we work every single day to craft products that enrich people’s lives. Do you love leading teams on challenges that no one has solved yet? Do you enjoy working with cross-functional teams to deliver IP solutions for products that impacts customers’ lives? We have an opportunity for a talented senior validation and characterization engineer to lead post silicon IP validation efforts. As a technical lead in an IP validation team, you will have the rare and rewarding opportunity to validate innovative analog/mixed-signal IPs in Apple’s products that will delight and inspire millions of customers. You will also play a very hands-on role in debug, stressing, and data analysis on the performance of analog/mixed-signal IPs for Apple’s world-class SOCs.

Key Qualifications

  • The ideal candidate should have the following qualifications:
  • Expertise in first silicon bring up, debug, validation and characterization
  • Good understanding of analog/mixed-signal circuits including high speed data converters, PLLs, DLLs, filters
  • Excellent programming skills developing automated test program for characterization, Python preferred
  • Probing techniques and signal integrity of high-speed transmission lines
  • High speed measurements in both time and frequency domain
  • Familiarity with measurement equipment including signal generators, spectrum analyzers, logic analyzers and scopes
  • Experience working with multi-discipline development team including IC design, PCB development, automated test equipment (ATE)


In this role, the key responsibilities are the following: Drive development of measurement tools and data collection automation Lead post silicon characterization and validation efforts of analog/mixed-signal IPs Work closely with IC design, product, and test engineering Develop understanding of the IP architecture/design and application of the IPs in an SoC/System Collaborate with design team to improve test/debug architecture Define and develop methods for stress testing to identify IP failure limits

Education & Experience

Requires BSEE or MSEE degree. Preferably 5+ years of relevant experience.

Additional Requirements