Digital Circuits Debug Engineer
Santa Clara Valley (Cupertino), California, United States
Do you have a passion for crafting entirely new solutions? As part of our Digital group, you’ll take imaginative and revolutionary ideas and determine how to turn them into reality! You and your team will apply engineering fundamentals and start from scratch if needed, bringing forward-thinking ideas to the real world. Your efforts will be groundbreaking. Join us, and you’ll help design the tools that allow us to bring customers experiences they’ve never before envisioned! You will join an exciting silicon design group that is responsible for designing innovative ASICs. We have an extraordinary opportunity for a circuit design engineer to lead the debug of advanced custom digital megacells (SRAM memories, on-chip sensors, ML accelerators data path) and enable successful ramp of our SOCs.
- We are looking for applicants with 5+ years design experience in advanced technology nodes.
- This is a hands-on role. You will perform independent simulation, analysis and data process to draw significant circuit insights.
- Experience in one or multiple of the following areas is highly desirable: SRAM circuits, custom circuit design, silicon debug.
- Understanding of CPU architecture is a plus.
- Deep understanding of deep sub-micron device physics, leakage mechanisms, technology interactions with device behavior.
- Ability to conduct experiments during silicon debug, gathering & analyzing data; and applying scripting to support efficient handling of ATE data.
- Ability to work seamlessly with multi-functional teams and bring results.
- Experience in scripting languages (Python /Perl or others) and CAD automation tools.
- Knowledge of industry standard circuit and design tools.
Imagine yourself at the center of our SOC design effort, collaborating with all fields, with a critical impact and playing a strategic role of getting functional products to millions of customers quickly. In this highly visible role, you will work on silicon char, ramp and debug efforts, collaborating with multi-functional teams on critical impact issues. You will be supporting mass production of Apple’s large volume marquee products, with the following responsibilities: Drive the silicon debug effort involving digital circuits. Work with circuit design teams to define the silicon characterization requirements. Engage with the PE/DFT teams to plan the silicon characterization for the test chips and product chips. Perform design analysis, modeling/simulation, spice simulation, statistical analysis and silicon bring up. Work closely with the systems lab to reproduce the circuit behavior using MBIST, functional diagnosis. Synthesize large volume of data and draw meaningful insights.
Education & Experience
BSEE / MSEE is required.