Front-End Methodology CAD Engineer - RTL Construction & Analysis

Beaverton, Oregon, United States


Role Number:200301320
Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you will help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You will ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you will be responsible for crafting and building the technology that fuels Apple’s devices. Together, we will enable our customers to do all the things they love with their devices! As a Front-End Methodology CAD Engineer, you will play a major role in promoting a reliable work environment for developing, maintaining, and improving automation software that design teams use for creating and modifying RTL. In addition, you will have the opportunity to support and develop Reset Domain Crossing (RDC), Clock Domain Crossing (CDC), and Lint applications for our SoCs across multiple design sites.

Key Qualifications

  • Typically requires at least 5+ years of relevant experience
  • Expertise in TCL and/or PERL is required
  • Expertise in Verilog System Verilog with experience in Verific-based Verilog parsers and elaborator
  • Experience in Reset-Domain-Crossing (RDC) and Clock-Domain-Crossing (CDC) methodologies and solutions
  • Source control system management (Perforce, Git) is a plus
  • Excellent communication, debug and root causing skills
  • History of evangelizing standard methodologies in software development, testing and regression infrastructure
  • Experience in developing software framework or flows is a plus


In this highly visible role, you will be: - Responsible for maintaining, developing, and improving our automation flows for constructing and modifying RTL for our SoCs designers across multiple sites - Responsible for developing, maintaining and enhancing our Reset Domain Crossing (RDC), Clock Domain Crossing (CDC), and Lint applications for our SoCs across multiple design sites - Apply your debugging experience to debug vendor tool problems and collaborate with designers to help solve their problems - Work closely with EDA vendor representatives to drive improvements and new methodologies - Participate in the automation of project creation and version control system work flows

Education & Experience

Bachelor's or Master's degree in a technical field

Additional Requirements