Cellular RF Systems Engineer – PLL

Santa Clara Valley (Cupertino), California, United States


Role Number:200301781
At Apple, we work every single day to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We invite you to join our dynamic group, for the unique and rewarding opportunity to contribute to upcoming products that will delight and inspire millions of Apple’s customers every day. Apple's RF Systems Engineering team is looking for a passionate, independent expert with a proven track record in the area of phase locked loops. Our world-class team shapes the mobile market with forward-thinking concepts while being fully accountable for execution and commitments on timeline and quality. Come and deliver leading-edge phase locked loops (PLLs) for Apple’s wireless products that enable a unique customer experience!

Key Qualifications

  • We would like you to have 7+ years of relevant experience in RF, including solid expertise in cellular PLL architectures.
  • You have extensive experience in specifying, simulating and designing PLLs and LO distribution including the mathematical background to define and assess the underlying algorithm and procedures.
  • You have strong understanding of frequency generation architectures, experience in analyzing crosstalk and coexistence scenarios and avoiding or mitigating them.
  • You have in-depth knowledge of cellular radio standards (GSM, UMTS, LTE, 5G NR), regulatory, and carrier requirements including their implications on PLL specifications.
  • Excellent communication skills, both written & verbal, would be very helpful.


In this role, you will be part of the best-in-class cellular RFSE Team. You will work closely with transmitter and receiver architecture teams, RF design teams, design and drive PLL innovations with focus on leading-edge performance under real-life conditions and clear differentiation from other solutions. Your daily work includes the following tasks: • Defining and specifying PLL and clocking architectures mainly for FR2 (mmW) • Break-down of overall PLL system requirements into requirements for the PLL building blocks. • This comprises budgeting of integrated phase noise (iPN), phase noise across the clocking architecture and crosstalk and coexisting analysis • Implementation and simulation of the PLL in the frequency-domain and in the time-domain using MATLAB. • Develop concepts to improve PLL phase noise performance and methods to reduce spurs. • Prepare specifications as input for design teams. • Align MATLAB models with measurement results.

Education & Experience

BSEE or MSEE is the foundation of your successful career to date. We would prefer a Ph.D. in electrical engineering or equivalent.

Additional Requirements