PMU Digital Design Intern (m/f/d)

Nabern, Baden-Wurttemberg, Germany


Role Number:200301805
At Apple, we believe our products begin with our people. By hiring a team with dynamic strengths, we drive creative thought. By giving that team everything they need, we drive innovation. By hiring incredible engineers, we drive precision. And through our process, we build memorable experiences for our customers. These elements come together to make Apple an amazing environment for motivated people to do the greatest work of their lives. You will become part of a hands-on development team that cultivates excellence, creativity and innovation. Can you imagine to be part of an innovative design team developing the next generation of revolutionary Apple products? The Power Management team is seeking a forward-thinking and innovative Digital Design Intern in our Nabern office close to Kirchheim Teck. In this role, you will be taking part in the design of our devices and assist with delivering high quality chips in order to meet performance, feature, timing, area, power and efficiency goals.

Key Qualifications

  • Coursework focusing on logic design techniques
  • Familiarity with RTL structures in Verilog or VHDL
  • Scripting language knowledge (Perl, Python or similar)
  • Ability to work efficiently in a team and be productive under tight schedules
  • Strong analytical and problem solving skills
  • An understanding of finite state machines, microcontroller architectures and mixed signal design
  • Available for 6 months or more


With mentorship, you will work within the Digital Design Team to refine or create requirements and specifications, collaborate with the Analog Design and Design Verification teams, create/update RTL designs, and run simulations to check your design. This internship could include tasks such as implementing bespoke control of analog circuits, creating state machines to control the system, or working on industry standard interfaces to high performance SoCs. Your designs will need to balance energy efficiency and area constraints with project schedule and maintainability. You may also review synthesis and power reports, root-cause and resolve timing and power issues and ensure maximal QoR throughout your design.

Education & Experience

Currently enrolled in your penultimate year of studies in a CE, EE, CS or related field (Bachelor's, Master's or PhD).

Additional Requirements

  • We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.