VLSI CAD Engineer – Noise and Timing for Gate-Level Flows and Methodologies

Austin, Texas, United States


Role Number:200305956
Do you love building elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You’ll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices. Together, you and your team will enable our customers to do all the things they love with their devices! In this role, you will be responsible for implementing and supporting flows and tools necessary to ensure clean noise and timing analysis for Apple silicon. As a CAD engineer working on noise and timing verification, you will work closely with design teams and CAD groups to ensure that our designs meet noise and performance goals.

Key Qualifications

  • The ideal candidate will have some exposure to noise and STA concepts, flows, and tools via relevant college-level course work. Background working in an EDA/CAD tool development/support role with hands-on experience in noise and STA flows is a definite plus.
  • Familiar with various aspects of noise and static timing analysis in deep sub-micron technologies
  • Familiar with analysis, tools, and methodologies for noise and timing closure
  • Good understanding of cross-talk, OCV effects, margins, and constraints
  • Programming in Perl, Python, Tcl, or other languages is a must
  • Good communicator who can accurately assess and describe issues to management and follow solutions through to completion
  • Familiarity with circuit modeling including SPICE models is a plus
  • Familiarity with software development life cycles, including documentation and testing


• Writing and supporting flows and tools around core gate-level noise and static timing analysis tools • Performing tool validation for noise and timing verification • Working with design teams to understand and debug issues related to constraints, flow scripts, noise, and timing closure • Deep analysis of noise violations and timing paths to identify key issues • Implement infrastructure/scripts to facilitate large scale noise and timing reports mining and visualization • Help create noise and timing ECO custom scripts for project tapeout • Working with Physical Design team, highlighting issues and best practices • Create documentation and help with guidelines/specs

Education & Experience

MS or BS Degree in technical discipline

Additional Requirements