Circuit Test Chip Design & Validation

Santa Clara Valley (Cupertino), California, United States


Role Number:200312574
Do you want to apply your engineering background to make big things happen? As part of our Digital Design Engineering group, you’ll take imaginative and revolutionary ideas and determine how to turn them into reality! You and your team will apply engineering fundamentals to bring forward-thinking ideas to the real world. You will join a hardworking circuit design team which delivers custom IP for pioneering Apple product ASICs. The IPs designed by your team go into CPU, GPU, SoC, Neural Engine and other critical parts of Apple product silicon. In this highly visible role, you will be responsible to thoroughly validate and characterize the custom IPs in silicon.

Key Qualifications

  • Good understanding of Device Physics/Transistor basics.
  • Good grasp of basic VLSI design concepts, 6T/8T memories, Reg files, Standard cells, P&R, timing and DFT.
  • Python, TCL and/or PERL programming experience.
  • System Verilog familiarity.
  • JTAG protocol understanding.
  • Preferred Skills:
  • Knowledge of TC1500 Protocol.
  • IEEE1687 (STAR SMS MBIST protocol).
  • Statistical data manipulation and reporting.
  • Experience with FPGA based systems.


Imagine yourself at the start of a fast-paced new design cycle. You will work with production chip architects, front end and DFT teams, custom IP design engineers, test & product engineers, silicon validation systems engineers to realize detailed testing of the new IPs in prototype silicon. You will draw on a broad set of skills you have gained as an electrical engineer and be required to find novel ways to test and debug new digital and AMS circuits. In this role you will: • Understand custom IPs – Memories/Digital circuits, AMS IPs and silicon validation requirements. • Understand architecture of testschips, IP chiplets and logic macro blocks in-depth. • Improve IP validation architecture in testchip with pathfinding and feedback from consumers. • Assist with improving overall testchip eco-system by implementing lessons learned. • Compose system requirements for silicon validation boards to test IPs. • Understand high level architecture & hierarchy of production chips. • Work with silicon test engineers to validate custom IPs in production chips. • Understand DFT DV test benches and modify to enable debug testing.

Education & Experience

BSEE / MSEE is preferred.

Additional Requirements