Digital Mixed Signal Modeling and Verification Engineer

Santa Clara Valley (Cupertino), California, United States


Role Number:200312818
Imagine what you could do here at Apple! Together we could help craft the next generation of the world’s finest devices. New ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your career, and there's no telling what you could accomplish. Our Digital Mixed Signal (DMS) Verification team is searching for a self-motivated, passionate individual for the role of DMS Modeling and Verification Engineer. We are looking for a strong candidate who can tackle diverse challenges in verifying digital/mixed-signal designs. In this highly visible role, you will be at the center of chip design efforts collaborating with multiple teams with a critical impact on getting functional products to millions of customers quickly. You will become part of a hands-on development team that fosters engineering excellence, creativity and innovation. Collaboration across teams is a key component of success at Apple. The right candidate will thrive in this type of environment. You will work with us from Apple's headquarters in Cupertino, California - it's one of the most exciting aspects of the job! Dynamic, inquisitive people and inspiring, innovative technologies are the norm here. Will you help us design the next generation of revolutionary Apple products?

Key Qualifications

  • 5+ years of proven experience in developing and verifying real-numbered analog and RF behavioral models in SystemVerilog
  • Proven understanding of SystemVerilog, RNM, UDN/UDT/UDR, wreal, and Verilog-AMS
  • Understanding of AMS and RF blocks like filters, ADC, DAC, VCO, A/DPLL, SerDes, LNA, Mixer, etc.
  • Working experience in Cadence Virtuoso Schematic Composer and ADE
  • Experience with Analog Assertion Based Verification
  • Experience in UVM TB development will be a strong plus
  • Experience in crafting synthesizable modeling is a plus
  • Experience in writing scripts in languages such as Perl or Python
  • Excellent teammate with excellent communication skills


As a Digital Mixed Signal (DMS) Modeling and Verification Engineer, you will be responsible for: - Developing accurate and simulation-efficient analog behavioral models for analog/RF blocks in SystemVerilog - Verifying that the behavior models are accurate representations of analog schematics - Integrating the models with RTL - Verifying analog functionalities against design specifications using analog behavioral models: for example, coding testbenches, test scenarios and assertions - Documenting modeling and verification results for formal review

Education & Experience

MSEE with 5 years of relevant experience

Additional Requirements