Front End Implementation CAD Engineer

Santa Clara Valley (Cupertino), California, United States
Hardware

Summary

Posted:
Role Number:200333842
Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You’ll ensure Apple products and services can seamlessly and expertly handle the tasks that make them beloved by millions. Joining this group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices. Together, you and your team will enable our customers to do all the things they love with their devices. This is a highly visible role on our Front-End CAD and Methodology team, responsible for Synthesis and Formal Equivalence flows. This role will have a critical impact on getting functional products to hundreds of millions of customers quickly.

Key Qualifications

  • 3+ years of experience in relevant field
  • Experience scripting in TCL, Perl, or Python
  • Basic understanding of digital design and VLSI concepts is required
  • Experience in Synthesis tools, such as Design Compiler, or RTL Compiler is required
  • Exposure to Machine Learning techniques strongly preferred
  • Experience in Physical Synthesis is a plus.
  • Experience with Formal equivalence tools such as Conformal LEC and/or Formality a plus.
  • Experience in linting, static timing analysis, power domain checking or place and route tools is a plus
  • Must have strong communication skills

Description

Responsible for developing, maintaining, and in some cases improving existing systems for Synthesis, Physical Synthesis, LEC, and Scan Insertion Support multiple design/integration teams and working with other CAD engineers to integrate your solutions in different flows. Will work on the state of the art power, performance, and area improvement techniques that show material improvement in silicon performance. Involve in developing in-house ML infrastructure to predict silicon performance and incorporate feedback in construction to optimize silicon. Perform Synthesis optimization algorithm analysis to study bottlenecks in performance and runtime. Survey research papers for new ideas and directions

Education & Experience

MSEE or BSEE

Additional Requirements