GPU Top RTL Engineer

Austin, Texas, United States
Hardware

Summary

Posted:
Weekly Hours: 40
Role Number:200367797
Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You’ll ensure Apple products and services can seamlessly and expertly handle the tasks that make them beloved by millions. Joining this group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices. Together, you and your team will enable our customers to do all the things they love with their devices At Apple, we push our designs to the limit in order to make amazing products. We want to delight our customers with hardware that performs great while delivering long battery life. As part of the mobile GPU design team, you will interface with Platform Architecture, Software, Design Verification, and Physical Design teams to deliver RTL and specifications for GPU power management, SOC interface logic, and shared IP. In addition, you will be responsible for integrating applicable IP from other teams to enable complete security, debug, and power management solutions.

Key Qualifications

  • Expertize in energy-efficient/low-power logic design
  • Strong understanding of logic optimization, synthesis, timing analysis, floor-planning, multiple voltage domains, and asynchronous clock crossings
  • Proficient in Verilog and/or System Verilog, UPF, and scripting languages
  • Familiarity with logic simulation and debug
  • Ability to work well in a team and be productive under aggressive schedules
  • 2+ years of industry experience preferred
  • Graphics hardware background a plus

Description

As a GPU Top RTL Integration Engineer you will: Deliver high quality RTL to Physical Design team Specify clock, power, and interface descriptions to ensure optimized design Integrate IP from other teams Close timing, power, area, and lint for design by optimizing RTL and constraints Collaborate effectively with IP teams spanning multiple sites.

Education & Experience

BS/MS CE or EE

Additional Requirements