FPGA Design Engineer

Santa Clara Valley (Cupertino), California, United States


Role Number:200390063
As a FPGA Design Engineer, you will work in a team developing custom tester solutions for Display products. You will integrate industry standard and custom hardware IP into SoCs. You will develop and maintain methodology and flows checks for your design. Collaborate with multi-disciplinary groups to make sure designs are delivered on time and with the highest quality by incorporating accurate checks at every stage of the design process.

Key Qualifications

  • Proven experience with design, bring up, debugging and verification on FPGA
  • Experience in large scale FPGA development for imaging / signal processing / embedded applications strongly preferred
  • Expertise in design and implementation of large SoCs
  • Broad knowledge and experience working with peripheral interfaces including SPI, USB, MIPI, I2C and on-chip bus protocols such as AMBA (AXI, AHB, APB)
  • Understanding of communication protocols including TCP/IP, UDP
  • Proven Experience with C++ and Python
  • Design and verification using Verilog/System Verilog
  • Perform FPGA Synthesis, Place & Route, timing optimizations
  • Perform bring-up, debug, and validation of designs to achieve functional and performance goals
  • Thoroughly document and support each of above steps
  • Collaborate with cross-functional teams in order to define prototype hardware to evaluate new technologies and features
  • 5+ years experience preferred


Create Field Programmable Gate Array (FPGA) models from a register transfer level (RTL) design using FPGA synthesis, partitioning and routing tools Develop hardware and software collaterals and integrate with the FPGA design Test and debug the FPGA designs and collaterals Define and develop new capabilities & HW/SW tools to enable acceleration of RTL and improve FPGA design usability for functional validation as well as software development/verification Micro-architecture and design of high-performance DMAs/data transfer engines/interconnects Computer architecture, SoC fabrics/interconnects, memory controllers, arbitration, flow control, caching, etc RTL design and verification System Verilog, scripting and modeling languages (e.g. Python, Perl, C) Verification test benches, coverage analysis, formal verification Collaboration, schedule and resource planning, task/team management skills

Education & Experience

MSEE or Equivalent required

Additional Requirements

Pay & Benefits