Sr. CAD Engineer – DV Methodology

Santa Clara Valley (Cupertino), California, United States


Role Number:200394835
Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You’ll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices. Together, you and your team will enable our customers to do all the things they love with their devices. As a member of our CAD team, you will develop, maintain, and enhance existing sophisticated software systems for regression-testing Apple’s silicon designs in software simulation, to find and report defects in our chip designs, and thus ensure that Apple tapes-out world-class silicon. Your experience and innovative ideas will inform the design of the next generation of these regression systems. Your experience and insight, your skill at diagnosing the root cause of complex problems, and your ability to guide engineers who come to you with problems will be important contributions to an extended CAD team that comprehensively supports Apple’s DV and chip design engineering efforts. You will work closely with EDA vendors to incorporate new capabilities of their commercial tools, and to resolve problems.

Key Qualifications

  • Typically requires at least 10+ years of experience with MSEE/CE/CS preferred.
  • Must be fluent in Verilog and SystemVerilog; familiarity with VHDL a plus.
  • Must be very experienced with Synopsys VCS, NC-Verilog, or Modelsim.
  • Strong scripting abilities in PERL are needed; TCL or Python is a plus.
  • Good communications skills are required and prior customer support experience is a plus.
  • Experience writing or maintaining the script or Makefile that builds the simulation
  • program from RTL is a plus.
  • Familiarity with Verdi and/or SimView is considered a plus.
  • Knowledge of C and C++ is a plus.


• Develop, maintain, and enhance an existing system for regressing RTL. • Role involves debugging vendor tool problems. • Interacting with DV team to help solve their problems. • Implement new functionality to solve emerging problems or to optimize already existing methods.

Education & Experience

BS or MS Degree in EE/CS or a technical field

Additional Requirements