Design Verification Engineer - Jerusalem
Jerusalem, Jerusalem District, Israel
In this visible role, you will be responsible for taking part of a SoC verification process of a large scale SoC. You will develop verification test plans, tools, test benches, protocol monitors, and high-coverage stimulus vectors. Apply advanced techniques to achieve verification with the highest quality, productivity, and time-to-market. You will work closely with the design team to ensure timely delivery of quality designs. Working with methods to accelerate verification time. Involvement in Post Silicon Validation.
- +3 years experience in SoC Verification.
- You will need to have advanced knowledge of SoC architecture/design & in-depth knowledge of verification flow.
- Expected to have a deep understanding and shown experience in advanced verification process, including dynamic, coverage based and formal methods.
- Familiarity with verification environments, UVM, SystemVerilog – an advantage.
- Knowledge of formal, hardware acceleration – an advantage.
- Scripting and programming experience using several of the following: Perl, e, Verilog, SystemVerilog, C, C++, and TCL.
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Education & Experience
B.Sc / M.Sc in Electrical or Computer Engineering