Wireless Design Verification Engineer
Beaverton, Oregon, United States
Imagine what you could do here at Apple! New ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Do you love working on challenges that no one has solved yet? Bring passion and dedication to your career, and there's no telling what you could accomplish. Our growing wireless silicon development team is pioneering the next generation of wireless silicon! In this role you, will be responsible for ASIC pre-silicon verification of extremely complex high throughput communication PHY and Radio sub-systems. You will develop innovative testbenches, enhance sophisticated methodologies, develop verification plans, debug functional tests, and apply coverage analytics. You will be in the center of the organization impacting and influencing many cross-functional teams.
- Significant experience verifying complex IP with a track record of robust ASICs
- Experience verifying Wireless or Digital Signal Processing (DSP) systems is significantly valued. Exposure to digital-radio and PLL controllers is a plus
- Advanced knowledge of ASIC verification flows with SystemVerilog and UVM
- Experience developing testbenches from scratch, bringing up designs in simulation
- Skills with constrained random testing, coverage closure, and RTL simulations
- Proficient in a scripting language such as Python, Perl, Bash or similar
- Phenomenal teammate with excellent communication skills and the desire to seek diverse challenges
- Knowledge of a wireless protocol valued, e.g. Wi-Fi / IEEE 802.11, Bluetooth or LTE
This role will empower you to lead critical block or sub-system verification of PHY and/or Radio Controller (digital), and architect and develop testbenches and environments. You will create, simulate and debug test scenarios, and lead regressions and issue tracking. There will be collaboration with design and systems engineering teams to review specifications and architecture, extract features, and define verification plans. You'll drive coverage analysis and closure, and collaborate with / support digital + mixed-signal co-simulations using SystemVerilog analog behavioral models.
Education & Experience
BS + 10 years of relevant experience required.