CPU RTL Engineer (Load/Store)

Santa Clara Valley (Cupertino), California, United States


Role Number:200482857
Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hard-working people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products! The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver groundbreaking Apple products! Apple’s Silicon Engineering Group (SEG) is hiring dedicated engineers for CPU architecture and microarchitecture development with expertise in load/store execution and L1D cache management targeted for low power mobile devices.

Key Qualifications

  • Minimum BS and 10+ years of relevant industry experience
  • Thorough knowledge of microprocessor architecture including expertise in one or more of the following areas: out-of-order execution, load/store execution, cache and memory subsystems
  • Knowledge of Verilog and/or VHDL. Experience with simulators and waveform debugging tools.
  • Knowledge of logic design principles along with timing and power implications
  • Understanding of low power microarchitecture techniques
  • Understanding of high-performance techniques and trade-offs in a CPU microarchitecture
  • Experience in C or C++ programming
  • Experience using an interpretive language such as Perl or Python


As a RTL Engineer, you will own or participate in the following: Microarchitecture development and specification - from early high-level architectural exploration through micro architectural research and arriving at a detailed specification RTL ownership - development, assessment and refinement of RTL design to target power, performance, area and timing goals Validation - support test bench development and simulation for functional and performance verification Performance exploration and correlation - explore high performance strategies and validate that the RTL design meets targeted performance Design delivery - work with multifunctional engineering team to implement and validate physical design on the aspects of timing, area, reliability, testability, and power

Education & Experience

Minimum BS and 10+ years of relevant industry experience

Additional Requirements

Pay & Benefits