IC Packaging Engineer

Taipei, Taiwan, Taiwan
Hardware

Summary

Posted:
Weekly Hours: 40
Role Number:200499421
Imaging what you could do here. At Apple, creative ideas have a way of becoming wonderful products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. We believe this is an excellent opportunity to work on the New Technology project in the exemplary company consistently bringing innovations in the industry. We are looking for a senior level IC packaging engineer to develop exciting new products. Your role is to interface between internal product/device design, quality, supply chain, and the external suppliers to develop and deploy new packaging technologies. We are looking for individuals who are very innovative with a proven track record to bring packaging solution from concept to high-volume manufacturing.

Description

Define new package special characteristics based on unique module and system level performance, cost, and footprint requirements. Define package/packaging specifications. Work with foundry & assembly suppliers on advanced 2.5D/3D package development from design, new material, new equipment selection and establish robust process/process flow. Perform initial proof of concept sample build, process of record, package and process qualification, reliability test, yield analysis and continuous improvement. Interface and coordinate with other packaging team members to comply with product development/ramp schedule. Deliver package/packaging milestones on time. Define packaging roadmap based on long term packaged product requirements. Work closely and manage suppliers’ R&D activities. At least 5~10% travel to domestic and international locations.

Minimum Qualifications

Key Qualifications

  • In-depth knowledge in Die to Wafer, Wafer to Wafer bonding and RDL Fanout technologies inclusive of process and product integration.
  • Hands-on knowledge in key wafer process building blocks such as hybrid bonding, dielectric deposition/planarization/treatment and Cu RDL.
  • Good understanding to the knowledge in advanced silicon node BEOL and knowledge to device physics or component/board level reliability testing is a plus.
  • Proven track record to drive issue resolution with good understanding to root cause and physics, motivate and mobilize all levels within supplier to accomplish any given task. Able to perform independent research and development work with minimal supervision.
  • Good written and verbal communication skills. Able to present ideas, design concepts, data and plan with high confidence at internal or external meetings.

Preferred Qualifications

Education & Experience

M.S or Ph.D. degree in mechanical engineering, physics, materials science or similar disciplines with a minimum of 10 years of experience in IC packaging.

Additional Requirements