CAD Engineer –Analog Power Intent CAD & Methodology Engineer
San Diego, California, United States
Hardware
Do you love building elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You’ll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices. Together, you and your team will enable our customers to do all the things they love with their devices!
As a member of our CAD team, you will architect, dictate, develop, maintain and enhance custom analog power intent methodology and circuit ERC solutions for our Analog, RF and mixed-signal designs. The role requires you to work with different technology nodes and provide flows/methodologies for the different tool sets.
Key Qualifications
- Experience in Electric Rules Checks (ERC), circuit tracing and/or experience on custom power intent tools, flows and methodology.
- Analog/RFIC design background and/or related CAD/automation support areas involving various technology nodes and tape out.
- Knowledge on the operating principles of common Analog, and AMS blocks, Spice Modeling in Nano CMOS technologies. Schematic/layout tracing via SPICE/Open Access, power gating techniques, biasing, circuit topologies (power switches, level-shifter, iso), virtual/derived/multi-power domains, standard-cells.
- Hands on experience with Liberty/.lib, UPF - IEEE1801, CPF formats with exposure on power intent domain and methodology.
- Exposure to industry low power tools, Cadence Conformal LEC, Virtuoso Power Manager, Innovus; Synopsys Library compiler, VCLP, Low Power verification is desirable, Calibre PERC.
- Knowledge of Cadence Virtuoso Framework with experience on front end Schematic composer will helpful. Background in SPICE simulation, SOA, device operating conditions, and knowledge of Post-layout extraction is a plus.
- Efficient programming skills in Perl, Python, TCL, SKILL language, C++ or Shell. Ability to provide automations for rapid and dynamic design needs.
- Good written and verbal communication skills, and the ability to collaborate well with cross-functional teams.
Description
- Directly influence the advancement of a variety of technology nodes and develop/support flows on analog circuit topology and electrical rule checks.
- You will have an impact with the analog, mixed-signal, and RF circuit design teams. Drive and oversee efforts developing and validating custom circuit checker flows, improving custom design environment, validating checks and doing results analysis as you partner with layout design, technology, and 3rd party EDA tool vendors.
- Work on circuit topology identification, recognition, netlist tracing to find design issues while developing internal solutions.
Education & Experience
Minimum requirement of BS + 3 years of relevant industry experience.