ASIC Design Engineer
Cupertino, California, United States
Hardware
As an ASIC Design Engineer, the individual’s primary responsibility will be RTL design. This will include chip architecture definition, block/function definition, specification, design, simulation and unit level verification of digital functions on Mixed Signal ASICs.
Key Qualifications
- Proven track-record in digital design including RTL design experience
- Strong understanding of digital design flow including RTL simulation, logic synthesis, timing constraints, timing closure, STA, back annotation of parasitics, gate level simulation, equivalence checking
- Defining methodology and creating infrastructure to support FPGA based prototyping
- Flow automation scripts using Perl/Python, Tcl, and shell scripts
- Experience in Low Power is desired
- Power user of industry standard RTL Design & Synthesis tools. Knowledge of Extraction and STA methodology and tools
- Knowledge of best practices with respect to implementation of digital logic
- Experience in DisplayPort or DSP is preferred
- Understanding of Design Verification and the ability to write self-checking test suites
- Experience in hands-on lab evaluation and silicon bringup
- Understanding of ASIC test methodology such as scan insertion, memory BIST and test pattern generation
Description
Work with system and architecture teams to understand the top level requirements of the digital functions and develop detailed specifications
Implement the function in Verilog RTL to specification Perform unit level testing on the RTL function
Support the DV team by writing self-checking tests as required
Support all design integration activities like Lint, CDC, Synthesis & ECO
Work with Physical Design Team on STA, physical, power and logical issues
Education & Experience
BS+ 10 years of relevant experience. MS preferred.