Performance Model Integration Engineer, Platform Architecture
Seattle, Washington, United States
Hardware
Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products very quickly. Bring passion and dedication to your job and there's no telling what we can accomplish together.
Do you love crafting elegant solutions to highly complex challenges? Can you intrinsically see the importance of every detail? At Apple, our Platform Architecture group is responsible for connecting our hardware and software into one unified system. Join this team, and you'll collaborate with engineers across Apple to build and deploy forward-looking prototype systems that contribute to the development of our world renowned hardware and software architecture. This multi-disciplinary role ties together analysis from low level software tuning for custom CPU pipelines through SOC level cache and memory subsystem performance.
You and your team will develop tools that are used to ensure that every product we make performs exactly as intended. Together, our work will be the reason millions of customers feel that they can trust our devices every single day.
Apple’s Platform Architecture group is seeking a performance model integration engineer, who will develop novel technologies for accelerating the development and verification of silicon. You will work with our world leading silicon engineering teams and firmware development teams on next generation chips, which end up in the hands of millions of users worldwide.
Key Qualifications
- Excellent HDL programming skills in Verilog/SystemVerilog
- Experience with SystemVerilog and DPI (C/C++) preferred
- Knowledge of Computer Architecture principles
- Strong debugging skills in both software and hardware
- Experience developing HDL based testbenches required (no UVM experience needed)
- Experience developing HDL based testbenches for Emulation / Acceleration strongly preferred
- Experience with developing bus functional models, and using Verification IP preferred
- Experience with C/C++ testbenches
- Familiarity with CPU, IP, SoC performance analysis, latency characterization preferred
- X86/ARM Assembly experience a plus
- Familiarity with Xcelium/Modelsim/Synopsis VCS a plus
- Experience with waveform debugging a plus
- Scripting/coding ability in Python a plus
- Excellent communication skills and prior customer support experience a plus
Description
Develop and maintain RTL-based systems performance models, integration CPU IP and peripheral components
Validate, own, and ship models to cross-functional internal customers
Support and clearly communicate with engineers from multiple disciplines (software, architecture, verification, and validation)
Debug functionality and performance of large IP-based systems using simulation
Work independently and manage deliverables to different teams
Excellent communication, analytical and documentation skills required
Occasional travel to development groups in the US and overseas
Education & Experience
BS degree with 3+ years of relevant experience