SoC Cache Architecture Performance Modeling Engineer, Platform Architecture

Beaverton, Oregon, United States


Role Number:200538444
Do you love crafting elegant solutions to complex problems? Do you enjoy learning how systems work from the big picture down to the smallest detail? As part of the SoC Performance group, you’ll work with a diverse set of cross-functional teams to help architect, optimize, and ship our industry-leading SoCs powering Apple products from iPhone to Apple Watch, iPad, Macs, and more! You’ll join a team of performance architects who deeply analyze the way our SoCs are used by real software, in order to ensure that software can harness the full power of our chips and to drive the design of future SoCs to be an even better match for real-world use cases. We’re looking for experienced, passionate, and highly motivated individuals to help us set the standard on the performance, efficiency, and hardware/software integration of Apple’s products! You will enjoy this role if: - You're interested in hardware design, hardware/software co-design, hardware/software optimization, and power/performance tradeoffs. - You derive satisfaction from not only performing the analysis, but using your interpersonal skills to use your analysis to influence the direction of the organization. - You enjoy doing deep-dives into hardware and software parts that are outside of your immediate area of responsibility, to establish relationships across the organization and apply the findings to innovate the parts you own.

Key Qualifications

  • Ideally, you will have a B.S. and 10+ years of relevant industry experience and posses:
  • Good written and verbal communication skills.
  • Deep understanding of cache micro-architecture, data coherency protocols, and on-chip interconnect architecture.
  • Good knowledge of C++, including templates and the STL.
  • Experience in writing and using SoC performance models, and transforming the simulation results into compelling performance analysis.
  • Ability and enthusiasm to work with experts in other domains, such as CPU, GPU, Display, Camera, and Machine Learning, to understand their cache usage requirements, and help them apply good performance modeling practices to drive architecture and design decisions.
  • Proficiency in scripting languages, ideally Python.


As a SoC Cache Architecture Performance Modeling Engineer, you will collaborate with engineers across the organization to model and improve the hardware and low-level software architecture of our chips by using a high-performance C++ simulator. You will be involved with the full life-cycle of performance modeling, from early architectural exploration to post-silicon correlation. The role requires deep expertise in the architecture and design of SoC caches, how they are used by the different SoC components such as CPU, GPU, Display, Camera, Machine Learning, and how they interact with the other parts of the memory system. It also requires appreciating the good parts of C++, and using the language to enhance the utility of our simulation models.

Education & Experience

B.S. and 10+ years of relevant industry experience. Masters, or PhD in EE, CS, or related field preferred

Additional Requirements