SerDes Validation Engineer
Cupertino, California, United States
Hardware
In this role, the candidate will work within the Mac Hardware organization in the area of SerDes I/O validation for Mac Platforms . This will include I/O Compliance flow bringup, and execution of Mac platforms, enabling Stress testing of I/Os in systems, metrics as well as give to factory level eye-scan test flow development for high-volume data collection for IO design margin optimization. Come join our team!
Key Qualifications
- Lab skills: High speed oscilloscopes, BERT, logic analyzers, electronic loads, probing techniques
- Experience with high-speed serial I/O busses is required: example USB3, DisplayPort, Thunderbolt, PCIe
- Understanding of signal integrity concepts such as differential impedance, jitter, insertion loss, return loss, termination, etc
- Familiarity with electrical compliance test specifications (CTS) and compliance test suite.
- Basic surface mount component solder rework ability is a plus
- Experience with schematic and PCB physical design tools to interpret the design and locate physical probe points
- Excellent documentation and communication skills to coordinate and update on report status across a large number of tests and measurement results
- MacOS and command line interface experience are preferred
- Scripting experience in any programming language (C++, Python, PERL, MATLAB) to develop automation scripts is a plus
- Experience in Analog IP Characterization (SerDes, PLL, Data Converters, DDR) is desirable
- Deep understanding and working knowledge of register programming for configuring SerDes PHY and Controller blocks for system validation needs
- Experience in driving initiatives that improved process, procedures, and result quality of high Speed IO Validation at product level
Description
- Execute high-speed serial I/O electrical compliance tests
- Organize compliance data reports for comparison against specs and approval by certification orgs
- Troubleshoot and triage issues with compliance test hardware, fixtures, software, and the DUT (Device Under Test)
- Failure analysis feedback for iterative HW design/SW Tunable improvements
- Define and develop methods for stress testing to identify design operating limits of Serial IOs post system integration
- Develop deep understanding of details of the IP architecture/design
Education & Experience
- Minimum 5 years relevant industry work experience.
- Educational Qualification: BSEE is required, MSEE is a plus.